I am a PhD student in the Systems Research Group at TU Munich. I work on computer architecture, focusing on cache coherence protocols for heterogeneous systems and on memory disaggregation over scale-up interconnects such as CXL.
Every host speaks its own coherence protocol, while CXL speaks another. My research makes them interoperate, automatically and correctly: from a methodology to build CXL bridges (C3), to synthesizing and verifying them from specifications (vCXLGen), to generating coherence controllers for any protocol, topology, and policy (Synapse). I am now extending these bridges to GPUs and beyond a single rack.
Before TUM, my master's thesis at EPFL's Embedded Systems Laboratory mapped convolutional layers onto OpenEdgeCGRA, a low-power open-hardware CGRA. Feel free to reach out to collaborate or chat about research.
Ph.D. in Computer Science Technical University of Munich
Oct 2024 – exp. Oct 2028 · Advisor: Prof. Pramod Bhatotia
M.Sc. in Computer Engineering Politecnico di Torino
Oct 2021 – Mar 2024 · Thesis with the Embedded Systems Laboratory (ESL), EPFL, as a visiting student (2023–2024)
B.Sc. in Electronic Engineering Politecnico di Torino
Oct 2018 – Sep 2021
Automated synthesis of verified CXL bridges for heterogeneous architectures.
Distinguished Paper Award Candidate
Coherence controllers are hand-tailored to one protocol, topology, and policy. Synapse specifies the three independently and synthesizes verified, gem5-ready controllers for any combination.
Best Paper Award
Generates CXL bridges automatically from host and CXL protocol specifications, and verifies them compositionally.
A methodology to build host-specific CXL bridges that translate coherence requests while preserving each host's memory consistency model.
Brings GPUs into CXL multi-host coherent fabrics as first-class hosts, with a coherence bridge at the GPU L2 and local HBM repurposed as a cache for CXL memory.
vCXLGen: Automated Synthesis and Verification of CXL Bridges for Heterogeneous Architectures (invited extended version)
CXL-GPU: Cache-Coherent Memory Expansion for GPUs over CXL
Synapse: Decoupling Protocol, Topology, and Policy for Automated Synthesis of Coherence Controllers
IEEE/ACM MICRO 2026, Athens, Greece
Automated Synthesis of Verified CXL Bridges for Heterogeneous Architectures
DFG SPP 2377 “Disruptive Memory Technologies” Annual Meeting, Dresden, Germany
Systems Programming
Course Organizer, TUM
Introduction to Software Engineering (EIST)
Exam Team, TUM
Disaggregated, Vendor-Generic APUs with CXL
B.Sc. thesis of Victor Fritz Trost
Artifact Evaluation Committee
IEEE/ACM MICRO 2026
Artifact Evaluation Committee
ACM ASPLOS 2026
Distinguished Paper Award Candidate 2026
IEEE/ACM MICRO 2026 · Synapse
Student Travel Grant 2026
IEEE/ACM MICRO 2026
Best Paper Award 2026
ACM ASPLOS 2026 · vCXLGen
Induction in IEEE-HKN, Mu Nu Chapter 2022
Politecnico di Torino
I am a naturally curious person who likes to dissect problems. Outside engineering, my big passion is medicine: I grew up idolizing Dr. House and his way of diagnosing problems. To unwind I play sports, from skiing and tennis to football, basketball, padel, and volleyball. Yes, I was a hyperactive kid. I also played piano and flute for over eight years.